1. Field of the Invention
The present invention relates to the testing of microprocessors. It more specifically relates to a device and a method for, in a monitoring circuit integrated in a microprocessor chip, storing digital messages enabling following the operation of the microprocessor before transmitting the messages to an external analysis tool.
2. Discussion of the Related Art
FIG. 1 schematically shows an integrated circuit 10 comprising a microprocessor (μP) 12, an internal memory (MEM) 14, and input/output terminals (I/O)16. Microprocessor 12 is intended to execute a program or software stored in memory 14. Under control of the program, microprocessor 12 may process data provided by input/output terminals 16 or stored in memory 14 and reading or writing data through input/output terminals 16.
To check the proper operation of the microprocessor, a monitoring circuit 18 is generally integrated on integrated circuit 10. Monitoring circuit 18 is capable of reading specific data provided by microprocessor 12 on execution of a program, and of possibly performing a processing on the read data. Test terminals 22 connect monitoring circuit 18 to an analysis tool 24. Analysis tool 24 may perform a processing of the received signals, for example, according to commands provided by a user, and ensure a detailed analysis of the operation of microprocessor 12. In particular, analysis tool 24 may determine the program instruction sequence really executed by microprocessor 12.
The number of test terminals 22 for a conventional monitoring circuit 18 may be on the same order of magnitude as the number of input/output terminals 16 of microprocessor 12, for example, from 200 to 400. Test terminals 22 as well as the connections of monitoring circuit 18 take up a significant silicon surface area, which causes an unwanted increase in the circuit cost. For this purpose, a first version of integrated circuit 10 comprising monitoring circuit 18 and test terminals 22 is generated in small quantities to adjust the program of microprocessor 12 or “user program”. After this adjustment, a version of integrated circuit 10 without monitoring circuit 18 and without test terminals 22 is for sale. This requires providing two versions of the integrated circuit, which requires a significant amount of work and is relatively expensive. Further, the final chip is not necessarily identical to the tested chip.
To overcome the above-mentioned disadvantages, it is desired to form a monitoring circuit 18 which takes up a reduced surface area and only requires a reduced number of test terminals 22, which decreases the cost of monitoring circuit 18. Monitoring circuit 18 can then be left on the finally sold integrated circuit 10.
It is thus desired to decrease the number of signals provided by monitoring circuit 18. For this purpose, certain logic operations are directly performed at the level of monitoring circuit 18 on the data measured at the level of microprocessor 12 to only transmit messages having an important information content.
Thus, standard IEEE-ISTO-5001, in preparation1 provides in its 1999 version, accessible, for example, on website www.ieee-isto.org/Nexus5001, a specific message exchange protocol between a monitoring circuit and an analysis tool for a monitoring circuit 18 requiring but a reduced number of test terminals 22.
The monitoring circuit is provided to monitor the microprocessor operation and to provide the test terminals with predetermined messages corresponding to the execution of certain instructions only. Other messages correspond to the execution of certain instructions in certain predetermined conditions. The different types of messages and their structure are described in section 6 of standard IEEE-ISTO-5001.
Several messages may be provided within a reduced time interval. According to the standard; each new message is stored in a box, or storage area of predetermined size, of a buffer memory of first-in/first-out type (FIFO) when the test terminals are not available (when they are used to transmit another previously-generated message), after which the message is sent to the analysis tool, and the memory box is freed, when the test terminals are available. The buffer memory comprises a number n of boxes which depends on the frequency at which the messages can be written into the buffer memory and of course also of the frequency at which the buffer memory is read, and on the number of used test terminals.
Certain microprocessors can execute in parallel several instructions of the program. For example, a jump instruction can be executed simultaneously with a instruction for reading from and/or writing into memory 14. In such a case, two or three messages are generated at the same time. To store several messages generated at the same time, a solution consists of storing these messages at the same time in a same box of the buffer memory. This compels increasing the storage capacity of each box and thus of increasing the size of the buffer memory. This problem is all the greater as the microprocessor is capable of executing a large number of instructions at the same time. Further, according to the standard, an execution of the same instruction can generate messages of different types.